1. Field of the Invention
The present invention relates in general to programmable delay circuits and in particular to a system for linearizing a programmable delay circuit so that its delay is a linear function of the value of its input control data.
2. Description of Related Art
A typical prior art programmable delay circuit includes a tapped delay line and a multiplexer. The delay line is formed by a set of delay stages connected in series for successively delaying an input signal pulse. Each delay stage may, for example, be a simple logic gate passing its input signal to its output with a delay depending on the switching speed of the logic gate. With the output of each delay stage constituting a separate "tap" of the delay line, the input signal pulse appears at each tap in succession as it traverses the delay line. The delay line taps are connected to separate inputs of the multiplexer for selectively linking one of the delay line taps to the delay circuit's output terminal. An input signal supplied to the delay line therefore passes through one or more delay stages to a selected tap, then passes through the multiplexer to appear as the delay circuit's output signal. The delay between edges of the input and output signal is therefore a function of the control data supplied to the multiplexer.
We normally want the delay provided by a delay circuit to be a linear function of its input control data. If all elements of the delay line had the same unit delay, then the total delay provided by the programmable delay circuit would be a linear function of the number of delay elements the input signal passes through before reaching the selected tap. Therefore the circuit's delay would be a linear function of the value of the control data. However even though delay elements are formed by similar logic gates formed on the same integrated circuit, due to process variations all gates will not have exactly the same switching speed. Such variation in gate switching speed adversely affects the linearity of the delay circuit's delay as a function of the control data supplied to the multiplexer.
U.S. Pat. No. 5,963,074 issued Oct. 5, 1999 to Brian J. Arkin, describes a programmable delay circuit of the type including a tapped delay line for delaying an input signal pulse to produce a set of tap signals selected by a multiplexer. However Arkin's programmable delay circuit also includes a "delay adjustment stage" between the output of the multiplexer and the delay circuit output terminal for finely adjusting the circuit delay. Thus the total delay of the circuit is equal to the sum of the delay through the selected tap, the inherent delay of the multiplexer, and the delay through the delay adjustment stage. A random access memory read addressed by input control data stores at each address "COARSE" control data for controlling the multiplexer and "FINE" control data for controlling the delay of the delay adjustment stage. Thus when the RAM is addressed by input control data, the RAM reads out COARSE and FINE control data in the addressed storage location which sets the delay of the circuit.
Arkin teaches that the total delay of the circuit can be made a linear function of the input control data by appropriately adjusting the values of the COARSE and FINE control data stored at each RAM address. One way to do that is to use an oscilloscope or other device to iteratively measure a timing difference between clock and output signal pulses for each value of input control data and to adjust the COARSE and FINE data values stored at the each RAM address until that each input control data value produces the appropriate delay. However such a labor-intensive process is tedious, time consuming and subject to error.
What is needed is an automatic system for quickly and accurately adjusting the data stored in the RAM so that the circuit delay is a linear function of the input control data addressing the RAM.